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? semiconductor components industries, llc, 2001 october, 2001 rev. 3 1 publication order number: uc3842a/d uc3842a, uc3843a, uc2842a, uc2843a high performance current mode controllers the uc3842a, uc3843a series of high performance fixed frequency current mode controllers are specifically designed for offline and dctodc converter applications offering the designer a cost effective solution with minimal external components. these integrated circuits feature a trimmed oscillator for precise duty cycle control, a temperature compensated reference, high gain error amplifier, current sensing comparator, and a high current totem pole output ideally suited for driving a power mosfet. also included are protective features consisting of input and reference undervoltage lockouts each with hysteresis, cyclebycycle current limiting, programmable output deadtime, and a latch for single pulse metering. these devices are available in an 8pin dualinline plastic package as well as the 14pin plastic surface mount (so14). the so14 package has separate power and ground pins for the totem pole output stage. the ucx842a has uylo thresholds of 16 v (on) and 10 v (off), ideally suited for offline converters. the ucx843a is tailored for lower voltage applications having uvlo thresholds of 8.5 v (on) and 7.6 v (off). ? trimmed oscillator discharge current for precise duty cycle control ? current mode operation to 500 khz ? automatic feed forward compensation ? latching pwm for cyclebycycle current limiting ? internally trimmed reference with undervoltage lockout ? high current totem pole output ? undervoltage lockout with hysteresis ? low startup and operating current ? direct interface with on semiconductor sensefet products http://onsemi.com 14 so14 d suffix case 751a 1 see detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet. ordering information see general marking information in the device marking section on page 16 of this data sheet. device marking information 1 8 pdip8 n suffix case 626 pin connections (top view) v ref (top view) compensation voltage feedback current sense r t /c t v ref v cc output gnd 1 2 3 45 6 7 8 compensation nc voltage feedback nc current sense nc r t /c t nc v cc v c output gnd power ground 1 2 3 4 5 6 7 9 8 10 11 12 13 14 1 8 so8 d1 suffix case 751
uc3842a, uc3843a, uc2842a, uc2843a http://onsemi.com 2 figure 1. simplified block diagram 5.0v reference latching pwm v cc undervoltage lockout oscillator error amplifier 7(12) v c 7(11) output 6(10) power ground 5(8) 3(5) current sense input v ref 8(14) 4(7) 2(3) 1(1) gnd 5(9) r t c t voltage feedback input r r + - v ref undervoltage lockout output compensation pin numbers in parenthesis are for the d suffix so-14 package. v cc maximum ratings rating symbol value unit bias and driver voltages (zero series impedance, see also total device spec) v cc , v c 30 v total power supply and zener current (i cc + i z ) 30 ma output current, source or sink (note 1) i o 1.0 a output energy (capacitive load per cycle) w 5.0 m j current sense and voltage feedback inputs v in 0.3 to + 5.5 v error amp output sink current i o 10 ma power dissipation and thermal characteristics d suffix, plastic package maximum power dissipation @ t a = 25 c thermal resistance, junctiontoair n suffix, plastic package maximum power dissipation @ t a = 25 c thermal resistance, junctiontoair p d r q ja p d r q ja 862 145 1.25 100 mw c/w w c/w operating junction temperature t j + 150 c operating ambient temperature uc3842a, uc3843a uc2842a, uc2843a t a 0 to + 70 25 to + 85 c storage temperature range t stg 65 to + 150 c 1. maximum package power dissipation limits must be observed.
uc3842a, uc3843a, uc2842a, uc2843a http://onsemi.com 3 electrical characteristics (v cc = 15 v, [note 2], r t = 10 k, c t = 3.3 nf, t a = t low to t high [note 3], unless otherwise noted.) uc284xa uc384xa characteristics symbol min typ max min typ max unit reference section reference output voltage (i o = 1.0 ma, t j = 25 c) v ref 4.95 5.0 5.05 4.9 5.0 5.1 v line regulation (v cc = 12 v to 25 v) reg line 2.0 20 2.0 20 mv load regulation (i o = 1.0 ma to 20 ma) reg load 3.0 25 3.0 25 mv temperature stability t s 0.2 0.2 mv/ c total output variation over line, load, temperature v ref 4.9 5.1 4.82 5.18 v output noise voltage (f = 10 hz to 10 khz, t j = 25 c) v n 50 50 m v long term stability (t a = 125 c for 1000 hours) s 5.0 5.0 mv output short circuit current i sc 30 85 180 30 85 180 ma oscillator section frequency t j = 25 c t a = t low to t high f osc 47 46 52 57 60 47 46 52 57 60 khz frequency change with voltage (v cc = 12 v to 25 v) d f osc/ d v 0.2 1.0 0.2 1.0 % frequency change with temperature t a = t low to t high d f osc/ d t 5.0 5.0 % oscillator voltage swing (peaktopeak) v osc 1.6 1.6 v discharge current (v osc = 2.0 v) t j = 25 c t a = t low to t high i dischg 7.5 7.2 8.4 9.3 9.5 7.5 7.2 8.4 9.3 9.5 ma error amplifier section voltage feedback input (v o = 2.5 v) v fb 2.45 2.5 2.55 2.42 2.5 2.58 v input bias current (v fb = 2.7 v) i ib 0.1 1.0 0.1 2.0 m a open loop voltage gain (v o = 2.0 v to 4.0 v) a vol 65 90 65 90 db unity gain bandwidth (t j = 25 c) bw 0.7 1.0 0.7 1.0 mhz power supply rejection ratio (v cc = 12 v to 25 v) psrr 60 70 60 70 db output current sink (v o = 1.1 v, v fb = 2.7 v) source (v o = 5.0 v, v fb = 2.3 v) i sink i source 2.0 0.5 12 1.0 2.0 0.5 12 1.0 ma output voltage swing high state (r l = 15 k to ground, v fb = 2.3 v) low state (r l = 15 k to v ref , v fb = 2.7 v) v oh v ol 5.0 6.2 0.8 1.1 5.0 6.2 0.8 1.1 v 2. adjust v cc above the startup threshold before setting to 15 v. 3. low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. t low =0 c for uc3842a, uc3843a t high = +70 c for uc3842a, uc3843a 25 c for uc2842a, uc2843a +85 c for uc2842a, uc2843a
uc3842a, uc3843a, uc2842a, uc2843a http://onsemi.com 4 electrical characteristics (v cc = 15 v, [note 4], r t = 10 k, c t = 3.3 nf, t a = t low to t high [note 5], unless otherwise noted.) uc284xa uc384xa characteristics symbol min typ max min typ max unit current sense section current sense input voltage gain (notes 6 & 7) a v 2.85 3.0 3.15 2.85 3.0 3.15 v/v maximum current sense input threshold (note 6) v th 0.9 1.0 1.1 0.9 1.0 1.1 v power supply rejection ratio v cc = 12 to 25 v (note 6) psrr 70 70 db input bias current i ib 2.0 10 2.0 10 m a propagation delay (current sense input to output) t plh(in/out) 150 300 150 300 ns output section output voltage low state (i sink = 20 ma) low state (i sink = 200 ma) high state (i sink = 20 ma) high state (i sink = 200 ma) v ol v oh 13 12 0.1 1.6 13.5 13.4 0.4 2.2 13 12 0.1 1.6 13.5 13.4 0.4 2.2 v output voltage with uvlo activated v cc = 6.0 v, i sink = 1.0 ma v ol(uvlo) 0.1 1.1 0.1 1.1 v output voltage rise time (c l = 1.0 nf, t j = 25 c) t r 50 150 50 150 ns output voltage fall time (c l = 1.0 nf, t j = 25 c) t f 50 150 50 150 ns undervoltage lockout section startup threshold ucx842a ucx843a v th 15 7.8 16 8.4 17 9.0 14.5 7.8 16 8.4 17.5 9.0 v minimum operating voltage after turnon ucx842a ucx843a v cc(min) 9.0 7.0 10 7.6 11 8.2 8.5 7.0 10 7.6 11.5 8.2 v pwm section duty cycle maximum minimum dc max dc min 94 96 0 94 96 0 % total device power supply current (note 4) startup: (v cc = 6.5 v for ucx843a, (v cc = 14 v for ucx842a) operating i cc 0.5 12 1.0 17 0.5 12 1.0 17 ma power supply zener voltage (i cc = 25 ma) v z 30 36 30 36 v 4. adjust v cc above the startup threshold before setting to 15 v. 5. low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. t low =0 c for uc3842a, uc3843a t high = +70 c for uc3842a, uc3843a 25 c for uc2842a, uc2843a +85 c for uc2842a, uc2843a 6. this parameter is measured at the latch trip point with v fb = 0 v. 7. comparator gain is defined as: a v d v output compensation d v current sense input
uc3842a, uc3843a, uc2842a, uc2843a http://onsemi.com 5 r t w , timing resistor (k ) figure 2. timing resistor versus oscillator frequency figure 3. output deadtime versus oscillator frequency figure 4. oscillator discharge current versus temperature figure 5. maximum output duty cycle versus timing resistor figure 6. error amp small signal transient response figure 7. error amp large signal transient response 0.5 m s/div 20 mv/div v cc = 15 v a v = -1.0 t a = 25 c 10 k 20 k 50 k 100 k 200 k 500 k 1.0 m f osc , oscillator frequency (hz) v cc = 15 v t a = 25 c 10 k 20 k 50 k 100 k 200 k 500 k 1.0 m f osc , oscillator frequency (hz) % dt, percent output deadtime v cc = 15 v t a = 25 c -55 -25 0 25 50 75 100 125 t a , ambient temperature ( c) , discharge current (ma) dischg i v cc = 15 v v osc = 2.0 v r t , timing resistor ( w ) 800 1.0 k 2.0 k 3.0 k 4.0 k 6.0 k 8.0 k , maximum output duty cycle (%) max d v cc = 15 v c t = 3.3 nf t a = 25 c i dischg = 9.5 ma i dischg = 7.2 ma 2.55 v 2.5 v 2.45 v v cc = 15 v a v = -1.0 t a = 25 c 0.1 m s/div 200 mv/div 2.5 v 3.0 v 2.0 v 80 50 20 8.0 5.0 2.0 0.8 100 50 20 10 5.0 2.0 1.0 9.0 8.5 8.0 7.5 7.0 100 90 80 70 60 50 40
uc3842a, uc3843a, uc2842a, uc2843a http://onsemi.com 6 figure 8. error amp open loop gain and phase versus frequency figure 9. current sense input threshold versus error amp output voltage figure 10. reference voltage change versus source current figure 11. reference short circuit current versus temperature figure 12. reference load regulation figure 13. reference line regulation d , output voltage change (2.0 mv/div) o 2.0 ms/div v d , output voltage change (2.0 mv/div) o 2.0 ms/div v v cc = 12 v to 25 v t a = 25 c d , reference voltage change (mv) ref 0 20 40 60 80 100 120 i ref , reference source current (ma) v v cc = 15 v t a = 55 c t a = 125 c , reference short circuit current (ma) sc -55 -25 0 25 50 75 100 125 t a , ambient temperature ( c) v cc = 15 v r l 0.1 w i v cc = 15 v i o = 1.0 ma to 20 ma t a = 25 c 0 -4.0 -8.0 -12 -16 -20 -24 110 90 70 50 t a = 25 c -20 a vol , open loop voltage gain (db) 10 m 10 f, frequency (hz) gain phase v cc = 15 v v o = 2.0 v to 4.0 v r l = 100 k t a = 25 c 0 30 60 90 120 150 180 100 1.0 k 10 k 100 k 1.0 m 0 20 40 60 80 100 , excess phase (degrees) f 0 v o , error amp output voltage (v) 0 , current sense input threshold (v ) v th 0.2 0.4 0.6 0.8 1.0 1.2 2.0 4.0 6.0 8.0 v cc = 15 v t a = 25 c t a = -55 c t a = 125 c
uc3842a, uc3843a, uc2842a, uc2843a http://onsemi.com 7 figure 14. output saturation voltage versus load current figure 15. output waveform figure 16. output cross conduction figure 17. supply current versus supply voltage 50 ns/div v cc = 15 v c l = 1.0 nf t a = 25 c 100 ns/div v cc = 30 v c l = 15 pf t a = 25 c , supply current 100 ma/div 20 v/div i , output voltage v cc o 800 600 400 200 0 i o , output load current (ma) , output saturation voltage (v) sat v v cc t a = 25 c t a = -55 c gnd t a = 25 c source saturation (load to ground) t a = -55 c v cc = 15 v 80 m s pulsed load 120 hz rate 010203040 , supply current (ma) cc v cc , supply voltage i r t = 10 k c t = 3.3 nf v fb = 0 v i sense = 0 v t a = 25 c ucx843a ucx842a 90% 10% 0 1.0 2.0 3.0 -2.0 -1.0 0 25 20 15 10 5 0 sink saturation (load to v cc )
uc3842a, uc3843a, uc2842a, uc2843a http://onsemi.com 8 + - sink only positive true logic = r s + internal bias reference regulator oscillator s r q - v ref uvlo 3.6v 36v v cc 7(12) q1 v in v cc v c 7(11) 6(10) 5(8) 3(5) + 1.0ma error amplifier 1(1) 2(3) 4(7) 8(14) 5(9) gnd output compensation voltage feedback input r t c t v ref - - pwm latch current sense comparator r r power ground current sense input 2r r 1.0v pin numbers in parenthesis are for the d suffix so-14 package. q t + - + + - + - + v cc uvlo output 2.5v figure 18. representative block diagram output/ compensation current sense input latch ``reset'' input output capacitor c t latch ``set'' input large r t /small c t small r t /large c t figure 19. timing diagram
uc3842a, uc3843a, uc2842a, uc2843a http://onsemi.com 9 operating description the uc3842a, uc3843a series are high performance, fixed frequency, current mode controllers. they are specifically designed for offline and dctodc converter applications offering the designer a cost effective solution with minimal external components. a representative block diagram is shown in figure 18. oscillator the oscillator frequency is programmed by the values selected for the timing components r t and c t . capacitor c t is charged from the 5.0 v reference through resistor r t to approximately 2.8 v and discharged to 1.2 v by an internal current sink. during the discharge of c t , the oscillator generates and internal blanking pulse that holds the center input of the nor gate high. this causes the output to be in a low state, thus producing a controlled amount of output deadtime. figure 2 shows r t versus oscillator frequency and figure 3, output deadtime versus frequency, both for given values of c t . note that many values of r t and c t will give the same oscillator frequency but only one combination will yield a specific output deadtime at a given frequency. the oscillator thresholds are temperature compensated, and the discharge current is trimmed and guaranteed to within 10% at t j = 25 c. these internal circuit refinements minimize variations of oscillator frequency and maximum output duty cycle. the results are shown in figures 4 and 5. in many noise sensitive applications it may be desirable to frequencylock the converter to an external system clock. this can be accomplished by applying a clock signal to the circuit shown in figure 21. for reliable locking, the freerunning oscillator frequency should be set about 10% less than the clock frequency. a method for multi unit synchronization is shown in figure 22. by tailoring the clock waveform, accurate output duty cycle clamping can be achieved. error amplifier a fully compensated error amplifier with access to the inverting input and output is provided. it features a typical dc voltage gain of 90 db, and a unity gain bandwidth of 1.0 mhz with 57 degrees of phase margin (figure 8). the noninverting input is internally biased at 2.5 v and is not pinned out. the converter output voltage is typically divided down and monitored by the inverting input. the maximum input bias current is 2.0 m a which can cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider source resistance. the error amp output (pin 1) is provide for external loop compensation (figure 31). the output voltage is offset by two diode drops ( 1.4 v) and divided by three before it connects to the inverting input of the current sense comparator. this guarantees that no drive pulses appear at the output (pin 6) when pin 1 is at its lowest state (v ol ). this occurs when the power supply is operating and the load is removed, or at the beginning of a softstart interval (figures 24, 25). the error amp minimum feedback resistance is limited by the amplifier's source current (0.5 ma) and the required output voltage (v oh ) to reach the comparator's 1.0 v clamp level: r f(min) 3.0 (1.0 v) + 1.4 v 0.5 ma = 8800 w current sense comparator and pwm latch the uc3842a, uc3843a operate as a current mode controller, whereby output switch conduction is initiated by the oscillator and terminated when the peak inductor current reaches the threshold level established by the error amplifier output/compensation (pin1). thus the error signal controls the peak inductor current on a cyclebycycle basis. the current sense comparator pwm latch configuration used ensures that only a single pulse appears at the output during any given oscillator cycle. the inductor current is converted to a voltage by inserting the ground referenced sense resistor r s in series with the source of output switch q1. this voltage is monitored by the current sense input (pin 3) and compared a level derived from the error amp output. the peak inductor current under normal operating conditions is controlled by the voltage at pin 1 where: i pk = v (pin 1) 1.4 v 3 r s abnormal operating conditions occur when the power supply output is overloaded or if output voltage sensing is lost. under these conditions, the current sense comparator threshold will be internally clamped to 1.0 v. therefore the maximum peak switch current is: i pk(max) = 1.0 v r s when designing a high power switching regulator it becomes desirable to reduce the internal clamp voltage in order to keep the power dissipation of r s to a reasonable level. a simple method to adjust this voltage is shown in figure 23. the two external diodes are used to compensate the internal diodes yielding a constant clamp voltage over temperature. erratic operation due to noise pickup can result if there is an excessive reduction of the i pk(max) clamp voltage. a narrow spike on the leading edge of the current waveform can usually be observed and may cause the power supply to exhibit an instability when the output is lightly loaded. this spike is due to the power transformer interwinding capacitance and output rectifier recovery time. the addition of an rc filter on the current sense input with a time constant that approximates the spike duration will usually eliminate the instability; refer to figure 27.
uc3842a, uc3843a, uc2842a, uc2843a http://onsemi.com 10 pin function description pin 8pin 14pin function description 1 1 compensation this pin is error amplifier output and is made available for loop compensation. 2 3 voltage feedback this is the inverting input of the error amplifier. it is normally connected to the switching power supply output through a resistor divider. 3 5 current sense a voltage proportional to inductor current is connected to this input. the pwm uses this information to terminate the output switch conduction. 4 7 r t /c t the oscillator frequency and maximum output duty cycle are programmed by connecting resistor r t to v ref and capacitor c t to ground. operation to 500 khz is possible. 5 gnd this pin is the combined control circuitry and power ground (8pin package only). 6 10 output this output directly drives the gate of a power mosfet. peak currents up to 1.0 a are sourced and sunk by this pin. 7 12 v cc this pin is the positive supply of the control ic. 8 14 v ref this is the reference output. it provides charging current for capacitor c t through resistor r t . 8 power ground this pin is a separate power ground return (14pin package only) that is connected back to the power source. it is used to reduce the effects of switching transient noise on the control circuitry. 11 v c the output high state (v oh ) is set by the voltage applied to this pin (14pin package only). with a separate power source connection, it can reduce the effects of switching transient noise on the control circuitry. 9 gnd this pin is the control circuitry ground return (14pin package only) and is connected back to the power source ground. 2,4,6,13 nc no connection (14pin package only). these pins are not internally connected. undervoltage lockout two undervoltage lockout comparators have been incorporated to guarantee that the ic is fully functional before the output stage is enabled. the positive power supply terminal (v cc ) and the reference output (v ref ) are each monitored by separate comparators. each has builtin hysteresis to prevent erratic output behavior as their respective thresholds are crossed. the v cc comparator upper and lower thresholds are 16 v/10 v for the ucx842a, and 8.4 v/7.6 v for the ucx843a. the v ref comparator upper and lower thresholds are 3.6v/3.4 v. the large hysteresis and low startup current of the ucx842a makes it ideally suited in offline converter applications where efficient bootstrap startup techniques are required (figure 34). the ucx843a is intended for lower voltage dc to dc converter applications. a 36 v zener is connected as a shunt regulator form v cc to ground. its purpose is to protect the ic from excessive voltage that can occur during system startup. the minimum operating voltage for the ucx842a is 11 v and 8.2 v for the ucx843a. output these devices contain a single totem pole output stage that was specifically designed for direct drive of power mosfets. it is capable of up to 1.0 a peak drive current and has a typical rise and fall time of 50 ns with a 1.0 nf load. additional internal circuitry has been added to keep the output in a sinking mode whenever an undervoltage lockout is active. this characteristic eliminates the need for an external pulldown resistor. the so14 surface mount package provides separate pins for v c (output supply) and power ground. proper implementation will significantly reduce the level of switching transient noise imposed on the control circuitry. this becomes particularly useful when reducing the i pk(max) clamp level. the separate v c supply input allows the designer added flexibility in tailoring the drive voltage independent of v cc . a zener clamp is typically connected to this input when driving power mosfets in systems where v cc is greater than 20 v. figure 26 shows proper power and control ground connections in a current sensing power mosfet application. reference the 5.0 v bandgap reference is trimmed to 1.0% tolerance at t j = 25 c on the uc284xa, and 2.0% on the uc384xa. its primary purpose is to supply charging current to the oscillator timing capacitor. the reference has short circuit protection and is capable of providing in excess of 20 ma for powering additional control system circuitry.
uc3842a, uc3843a, uc2842a, uc2843a http://onsemi.com 11 design considerations do not attempt to construct the converter on wirewrap or plugin prototype boards. high frequency circuit layout techniques are imperative to prevent pulsewidth jitter. this is usually caused by excessive noise pickup imposed on the current sense or voltage feedback inputs. noise immunity can be improved by lowering circuit impedances at these points. the printed circuit layout should contain a ground plane with lowcurrent signal and highcurrent switch and output grounds returning on separate paths back to the input filter capacitor. ceramic bypass capacitors (0.1 m f) connected directly to v cc , v c , and v ref may be required depending upon circuit layout. this provides a low impedance path for filtering the high frequency noise. all high current loops should be kept as short as possible using heavy copper runs to minimize radiated emi. the error amp compensation circuitry and the converter output voltage divider should be located close to the ic and as far as possible from the power switch and other noise generating components. current mode converters can exhibit subharmonic oscillations when operating at a duty cycle greater than 50% with continuous inductor current. this instability is independent of the regulators closedloop characteristics and is caused by the simultaneous operating conditions of fixed frequency and peak current detecting. figure 20a shows the phenomenon graphically. at t 0 , switch conduction begins, causing the inductor current to rise at a slope of m 1 . this slope is a function of the input voltage divided by the inductance. at t 1 , the current sense input reaches the threshold established by the control voltage. this causes the switch to turn off and the current to decay at a slope of m 2 until the next oscillator cycle. the unstable condition can be shown if a pertubation is added to the control voltage, resulting in a small d i (dashed line). with a fixed oscillator period, the current decay time is reduced, and the minimum current at switch turnon (t 2 ) is increased by d i + d i m2/m1. the minimum current at the next cycle (t 3 ) decreases to ( d i + d i m 2 /m 1 ) (m 2 /m 1 ). this pertubation is multiplied by m 2 .m 1 on each succeeding cycle, alternately increasing and decreasing the inductor current at switch turnon. several oscillator cycles may be required before the inductor current reaches zero causing the process to commence again. if m 2 /m 1 is greater than 1, the converter will be unstable. figure 20b shows that by adding an artificial ramp that is synchronized with the pwm clock to the control voltage, the d i pertubation will decrease to zero on succeeding cycles. this compensation ramp (m 3 ) must have a slope equal to or slightly greater than m 2 /2 for stability. with m 2 /2 slope compensation, the average inductor current follows the control voltage yielding true current mode operation. the compensating ramp can be derived from the oscillator and added to either the voltage feedback or current sense inputs (figure 33). figure 20. continuous current waveforms (a) (b) t 0 t 1 t 2 t 3 t 4 t 5 t 6 control voltage d i m1 m2 m3 m1 m2 oscillator period oscillator period control voltage d i inductor current d i + d i m 2 m 1 m 2 m 1 d i + d i m 2 m 1 inductor current
uc3842a, uc3843a, uc2842a, uc2843a http://onsemi.com 12 figure 21. external clock synchronization figure 22. external duty cycle clamp and multi unit synchronization figure 23. adjustable reduction of clamp level figure 24. softstart circuit figure 25. adjustable buffered reduction of clamp level with softstart figure 26. current sensing power mosfet virtually lossless current sensing can be achieved with the implementation of a sensefet power switch. for proper operation during over current conditions, a reduction of the i pk(max) clamp level must be implemented. refer to figures 23 and 25. the diode clamp is required if the sync amplitude is large enough to cause the bottom side of ct to go more than 300 mv below ground. external sync input 47 5(9) r r bias osc v ref r t 8(14) 4(7) 2(3) 1(1) 0.01 c t 2r r ea + - + 5(9) r r bias osc 8(14) 4(7) 2(3) 1(1) 2r r ea + - + 7 5.0k 3 8 6 5 1 c r s mc1455 2 r a + - + - 4 q 5.0k 5.0k r b to additional ucx84xa's f = 1.44 (r a + 2r b )c d max = r b r a + 2r b 5(9) r r bias osc 8(14) 4(7) 2(3) 1(1) 2r r ea + - + q1 r s 3(5) 5(8) 1.0v - r s q comp/latch 5.0v ref v clamp v in v cc 7(11) 6(10) - + + - + - + 7(12) + - r 1 r 2 r 2 v clamp = 1.67 + 1 + 0.33 x 10 - 3i pk(max) = vclamp rs where: 0 v clamp 1.0 v r2 r1 1.0ma r 1 r 1 + r 2 5(9) r r bias osc 8(14) 4(7) 2(3) 1(1) 2r r ea + - + 1.0v - r s q 5.0v ref - + + - + c t soft-start 3600c in m f 1.0m 1.0ma 5(9) r r bias osc 8(14) 4(7) 2(3) 1(1) 2r r ea + - + q1 r s 3(5) 5(8) 1.0v - r s q comp/latch 5.0v ref v clamp v in v cc 7(11) 6(10) - + + - + - + 7(12) + - mpsa63 r1 r2 c t softstart = - in 1 - v c r 1 r 2 c r 2 v clamp = 1.67 + 1 i pk(max) = vclamp rs where: 0 v clamp 1.0 v 1.0ma r 1 3v clamp r 1 + r 2 r s 1/4 w (5) (8) - r s q comp/latch 5.0v ref v in v cc (11) (10) - + + - + - + (12) + - power ground to input source return v pin 5 = if: sensefet = mtp10n10m r s = 200 then: v pin 5 = 0.075 i pk sensefet r s i pk r ds(on) m g d s k control circuitry ground: to pin (9) r dm(on) + r s
uc3842a, uc3843a, uc2842a, uc2843a http://onsemi.com 13 figure 27. current waveform spike suppression figure 28. mosfet parasitic oscillations figure 29. bipolar transistor drive figure 30. isolated mosfet drive figure 31. latched shutdown figure 32. error amplifier compensation the totem-pole output can furnish negative base current for enhanced transistor turn-off, with the addition of capacitor c 1 . error amp compensation circuit for stabilizing any current-mode topology except for boost and flyback converters operating with continuous inductor current. error amp compensation circuit for stabilizing current-mode boost and flyback topologies operating with continuous inductor current. the mcr101 scr must be selected for a holding of less than 0.5 ma at t a(min) . the simple two transistor circuit can be used in place of the scr as shown. all resistors are 10 k. series gate resistor r g will damp any high frequency parasitic oscillations caused by the mosfet input capacitance and any series wiring inductance in the gate-source circuit. the addition of the rc filter will eliminate instability caused by the leading edge spike on the current waveform. q1 r s 3(5) 5(8) - r s q comp/latch 5.0v ref v in v cc 7(11) 6(10) - + + - + - + 7(12) + - r c q1 r s 3(5) 5(8) - r s q comp/latch 5.0v ref v in v cc 7(11) 6(10) - + + - + - + 7(12) + - r g q1 r s 3(5) 5(8) v in 6(1) c 1 i b + 0 - base charge removal q1 3(5) 5(8) - r s q comp/latch 5.0v ref v in v cc 7(11) 6(1) - + + - + - + 7(12) + - n p r c r s n s isolation boundary v gs waveforms + 0 - + 0 - i pk = v (pin 1) - 1.4 3 r s n p n s 50% dc 25% dc 5(9) r r bias osc 8(14) 4(7) 2(3) 1(1) 2r r ea + - + 1.0ma 2n 3903 2n 3905 mcr 101 5(9) 2(3) 1(1) 2r r ea + - + 1.0ma c i r f r i r d from v o 2.5v 5(9) 2(3) 1(1) 2r r ea + - + 1.0ma c p c i r f from v o r p r d r i 2.5v
uc3842a, uc3843a, uc2842a, uc2843a http://onsemi.com 14 figure 33. slope compensation figure 34. 27 watt offline flyback regulator the buffered oscillator ramp can be resistively summed with either the voltage feedback or current sense inputs to provide slop e compensation. r i r d -3.0 m m 1.0v v in v cc r s 3(5) 5(8) 6(10) 7(11) 7(12) + - + - 5.0v ref bias osc 1.0ma + 2r r r r r s q c f r f ea 1(1) 2(3) 4(7) r t 8(14) mps3904 r slope from v o 5(9) c t comp/latch -m - + t1 - primary: 45 turns # 26 awg t1 - secondary 12 v: 9 turns # 30 awg t1 - (2 strands) bifiliar wound t1 - secondary 5.0 v: 4 turns (six strands) t1 - #26 hexfiliar wound t1 - secondary feedback: 10 turns #30 awg t1 - (2 strands) bifiliar wound t1 - core: ferroxcube ec35-3c8 t1 - bobbin: ferroxcube ec35pcb1 t1 - gap 0.01" for a primary inductance of 1.0 mh l1 - 15 m h at 5.0 a, coilcraft z7156. l2, l3 - 25 m h at 1.0 a, coilcraft z7157. comp/latch s r q 1n4935 1n4935 5.0v ref bias osc + + 47 100 ea + + 7(12) l1 5.0v/4.0a 2200 1000 + mur110 mbr1635 1000 1000 10 ++ + l2 5.0v rtn 12v/0.3a 1n4937 l3 mur110 12v rtn -12v/0.3a t1 1.0k 470pf 3(5) 5(8) 6(10) 7(11) 22 w 1n4937 2.7k 3300pf 4.7k 56k 250 + 115va c 4.7 w mda 202 68 5(9) + 1(1) 2(3) 4(7) 10k 0.01 4700pf 18k 4.7k mtp 4n50 8(14) 10 + + 680pf 0.5 w 150k 100pf + - + - + - - + + - + - - + test conditions results line regulation: 5.0 v 12 v v in = 95 vac to 130 vac d = 50 mv or 0.5% d = 24 mv or 0.1% load regulation: 5.0 v 12 v v in = 115 vac, i out = 1.0 a to 4.0 a v in = 115 vac, i out = 100 ma to 300 ma d = 300 mv or 3.0% d = 60 mv or 0.25% output ripple: 5.0 v 12 v v in = 115 vac 40 mv pp 80 mv pp efficiency v in = 115 vac 70% all outputs are at nominal load currents, unless otherwise noted.
uc3842a, uc3843a, uc2842a, uc2843a http://onsemi.com 15 ordering information device operating temperature range package shipping uc3842an pdip8 50 units/rail uc3842ad so14 55 units/rail uc3842adr2 so14 2500 tape & reel uc3843an t =0 to +70 c pdip8 50 units/rail uc3843ad t a = 0 to +70 c so14 55 units/rail uc3843adr2 so14 2500 tape & reel uc3843ad1 so8 98 units/rail uc3843ad1r2 so8 2500 tape & reel uc2842an pdip8 50 units/rail uc2842ad so14 55 units/rail uc2842adr2 so14 2500 tape & reel uc2843an t 25 to +85 c pdip8 50 units/rail uc2843ad t a = 25 to +85 c so14 55 units/rail uc2843adr2 so14 2500 tape & reel uc2843ad1 so8 98 units/rail uc2843ad1r2 so8 2500 tape & reel
uc3842a, uc3843a, uc2842a, uc2843a http://onsemi.com 16 x = 2 or 3 a = assembly location wl, l = wafer lot yy, y = year ww, w = work week so14 d suffix case 751a marking diagrams ucx84xad awlyww 14 1 uc384xan fawl yyww pdip8 n suffix case 626 uc284xan awl yyww 1 8 1 8 so8 d1 suffix case 751 alyw x843a 1 8
uc3842a, uc3843a, uc2842a, uc2843a http://onsemi.com 17 package dimensions pdip8 n suffix case 62605 issue l notes: 1. dimension l to center of lead when formed parallel. 2. package contour optional (round or square corners). 3. dimensioning and tolerancing per ansi y14.5m, 1982. 14 5 8 f note 2 a b t seating plane h j g d k n c l m m a m 0.13 (0.005) b m t dim min max min max inches millimeters a 9.40 10.16 0.370 0.400 b 6.10 6.60 0.240 0.260 c 3.94 4.45 0.155 0.175 d 0.38 0.51 0.015 0.020 f 1.02 1.78 0.040 0.070 g 2.54 bsc 0.100 bsc h 0.76 1.27 0.030 0.050 j 0.20 0.30 0.008 0.012 k 2.92 3.43 0.115 0.135 l 7.62 bsc 0.300 bsc m --- 10 --- 10 n 0.76 1.01 0.030 0.040 so14 d suffix case 751a03 issue f notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t t f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019
uc3842a, uc3843a, uc2842a, uc2843a http://onsemi.com 18 package dimensions so8 d1 suffix case 75107 issue w seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 x y g m y m 0.25 (0.010) z y m 0.25 (0.010) z s x s m
uc3842a, uc3843a, uc2842a, uc2843a http://onsemi.com 19 notes
uc3842a, uc3843a, uc2842a, uc2843a http://onsemi.com 20 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. uc3842a/d sensefet is a trademark of semiconductor components industries, llc. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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